Which Modules or Functions are Included in the FastChip Soft IP Library?

Triscend offers an extensive library of IP modules within the Triscend FastChip Development System. Below is the list of currently available IP modules along with the typical range for their respective Configurable System Logic utilization. Many of the IP modules are user-parameterizable, consequently the CSL count will vary with the application.

§ Serial Communication

o UART

§ Half-UART - Receive (34 - 152 CSL Cells)

§ Half-UART - Transmit (22 - 146 CSL Cells)

§ Full UART with Modem Control (152 - 360 CSL Cells)

o SPI

§ Master SPI (45 – 66 CSL Cells)

§ Slave SPI (172 – 478 CSL Cells)

§ Streaming SPI (65 – 123 CSL Cells)

o Baud Rate Generator (12 CSL Cells)

o Programmable Baud Rate Generator (21 CSL Cells)

o Two-wire Serial Interface (I²C-compatible)

§ Two-wire Master Only (256 CSL Cells)

§ Two-wire Slave Only (109 CSL Cells)

§ Two-wire Master/Slave (160 CSL Cells)

o HDLC Transmitter and Receiver (300 CSL Cells)

o Audio Interface

§ I2S Receiver (73 CSL Cells)

§ I2S Transmitter (90 CSL Cells)

o IrDA SIR Converter (23 CSL Cells)

§ Real-Time Clock (156 – 193 CSL Cells)

§ Logic Functions

o Reloadable Binary Counter (3 - 50 CSL Cells)

o Adder-Loadable (8 – 48 CSL Cells)

o Accumulator (8 – 48 CSL Cells)

o Comparator (8 CSL Cells)

o Multiplier, NxM, up to 16x16 (2 – 256 CSL Cells)

o Multiplier, NxM, pipelined, up to nx32 (2 – 2,048 CSL Cells)

o Multiplier, Constant Co-efficient (2 – 440 CSL Cells

o Data Register (1 – 32 CSL Cells)

o Divider, NxM, (2 – 2,048 CSL Cells)

o Shift Register (1 – 32 CSL Cells)

o Square Root (1 – 287 CSL Cells)

o Four-input LUT (1 CSL Cell)

o Constant (0 CSL Cells)

o Swapper (8 CSL Cells)

§ Memory

o Synchronous RAM (17 – 1,121 CSL Cells)

o Dual-Port RAM (16 – 1,120 CSL Cells)

o ROM (1 – 48 CSL Cells)

o FIFOs

§ Asynchronous FIFO (15 – 1140 CSL Cells)

§ Asynchronous Receive FIFO (16 – 1141 CSL Cells)

§ Asynchronous Transmit FIFO (16 – 1141 CSL Cells)

§ Req/Ack Receive FIFO (31 – 214 CSL Cells)

§ Transmit FIFO (33 –- 216 CSL Cells)

§ Display Driver

o 7 Segment Display (7 CSL Cells)

o LCD Character Display (13 CSL Cells)

o Graphic LCD Display Controller (120 – 350 CSL Cells)
(See AN20: Using the QVGA Graphics Controller Module)

§ Control

o Command Register (1 – 32 CSL Cells)

o Status Register (14 – 25 CSL Cells)

o Interrupt Expander (16 CSL Cells)
(See AN03: Using the Interrupt Expander Library Module)

o 8-bit Pulse Width Modulator (16 CSL Cells)

o Mailbox Interface (16 CSL Cells)

§ Pulse-Width Modulators (PWMs)

o 8-bit, from 2 to 8 bits (7 – 33 CSL Cells)

o 16-bit, from 9 to 16 bits (43 – 71 CSL Cells)

§ Encoders

o Bi-phase encoder, Manchester or BMC (5 – 6 CSL Cells)

§ Bus Interface

o AMBA Peripheral Bus (APB) (40 – 72 CSL Cells)

o 8-bit ISA Interface (11 CSL Cells)

o 8051-Style Multiplexed Address/Data Bus Interface

§ Audio Interface

o I2S Transmitter, 8 to 30 bit data (67 – 125 CSL Cells)

o I2S Receiver, 8 to 30 bit data (47 – 115 CSL Cells)

§ I/O

o Inputs/Outputs

o 3-State Outputs

o Bi-Directional

o 8051-style PIO Port (8 CSL Cells)

§ Interface Modules

o Ethernet

§ 10Base-T

§ E5: Interfacing the E5xx to an Integrated Ethernet 10Base-T MAC/PHY [Application Note AN-30]

§ A7: Interfacing an A7 to an Integrated Ethernet 10Base-T MAC/PHY [Application Note AN-40]

§ 10/100 Ethernet, Fast Ethernet

§ E5: Using a SMsC LAN91c110 or LAN91c111 with a Triscend E5 [Application Note AN-44]

§ A7: SmSC 10/100 Ethernet with the Triscend A7 [Application Note AN-45]

o CAN (45 CSL Cells)
(See AN31: Interfacing the E5xx to a CAN Controller)

o USB (30 CSL Cells)
(See AN19: Interfacing the E5xx to a USB Full-Speed Device Controller)

§ Encryption

o Triple DES (875 CSL Cells)

o Single DES ECB (731 CSL Cells)

o Single DES CBC (1,169 CSL Cells)

FastChip Version: 2.4.0

This solution may or may not apply to other versions of the FastChip development system.